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Lattice Semiconductor
CSIX Level 1 IP Core User’s Guide
Introduction
Lattice’s CSIX Level 1 core provides an ideal solution that meets the needs of today’s CSIX applications. The CSIX
Level 1 core provides a customizable solution allowing CSIX interfacing in many design applications. This core
allows designers to focus on the application rather than the CSIX interface, resulting in a faster time to market.
This User’s Guide explains the functionality of the CSIX Level 1 core and how it can be implemented to provide
CSIX interfacing for any application. It also explains how to achieve the maximum level of performance.
The CSIX Level 1 core comes with the documents and ?les listed below:
? Data sheet
? Encrypted gate level netlist
? Secured RTL simulation model
? Core instantiation template
Features
? Implements a CSIX-L1 to Generic FIFO Bridge
? Supports 32-bit, 100MHz CSIX-L1 Interface
? Up to Four Parameterizable 32-bit channel instantiations
? Parameterizable channel aggregation (32-bit to 128-bit)
? Parameterizable FIFO size (up to 2,048 bytes)
? Programmable FIFO thresholds
? Supports MAX_FRAME_PAYLOAD_SIZE from 1 to 256 bytes
? Transports unicast, multicast, broadcast, and ?ow control frames
? Filters idle frames (not transported through core)
? Delineates Cframes at Generic FIFO Bridge interface with Start/End Flags (SOF and EOF)
? Passes entire CSIX frame structure across Generic FIFO Bridge interface
? Passes CSIX link level control directly to Generic FIFO Bridge (bypasses FIFOs)
? Supports CSIX-L1 link-layer ?ow control (XON/XOFF)
? Programmable horizontal and vertical parity check enables
? Internal register set for control and status management
? 8-bit register interface compatible with ORCA System Bus
General Description
As stated by the CSIX Forum, the CSIX standard de?nes the physical and message layers of the interconnect
between traf?c managers (TM) and the switching fabric. The CSIX interface is designed to support a wide variety of
system architectures and markets, providing a framework with a common set of mechanisms for enabling a fabric
and a TM to communicate. This includes unicast addressing for up to 4,096 fabric ports, and multiple traf?c classes
that isolate data going to the same fabric port. Link level ?ow control is in-band and broken into a data and a control
queue to isolate traf?c based on this granular type. Flow control between the fabric and TM is de?ned and is rela-
tive to both fabric port and class. Three multicast approaches are de?ned. The interface assumes cell segmenta-
tion in the TM, but allows compression of the transfer.
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相关PDF资料
CSIX-PI40-O4-N1
INTERFACE IP CSIX TO PI40 ORCA 4
CT0805S14BAUTOG
VARISTOR 14VRMS 0805 SMD AUTO
CT1206K17G
VARISTOR 17VRMS 1206 SMD
CTB-B-B-15
CIRCUIT BREAKER ROCKER 15A SP BK
CU3225K17AUTOG2
VARISTOR AUTO 17VRMS 3225 SMD
CU3225K250G2K1
VARISTOR STD 250VRMS 3225 SMD
CV10-RP-M-0
CONN JACK STR COAXIAL SMD
CVM50XM
MEMBER MOD PIC12C508/PIC12C509
相关代理商/技术参数
CSIX-PI40-O4-N1
功能描述:输入/输出控制器接口集成电路 CSIX to PI40 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray
CSJ-100
制造商:GREENLEE TOOL CO 功能描述:Digital Open Jaw Clampmeter 制造商:Greenlee Textron Inc 功能描述:CLAMPMETER
CSJ-23
功能描述:EXTRACTION TOOL FOR SCS RoHS:否 类别:工具 >> 插入，抽取 系列:* 标准包装:1 系列:* 其它名称:0011-03-00080011-03-0008-E00110300080011030008-E11-03-0008-E1103000811030008-EQ4729393AT0980176A
CSJ32C1
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32C3
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32C5
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32E1
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals
CSJ32E3
制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals